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For Texas Instruments synchronous serial frame format, the SSPFSSOUT pin is pulsed for one
serial clock period starting at its rising edge prior to the transmission of each frame. For this
frame format, both the PrimeCell SSP and the off-chip slave device drive their output data on
the rising edge of SSPCLKOUT and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the National
Semiconductor Microwire format uses a special master-slave messaging technique which
operates at half-duplex. In this mode, an 8-bit control message is transmitted to the off-chip
slave when a frame begins. During this transmit, the SSP receives no incoming data. After the
message has been sent, the off-chip slave decodes it and responds with the requested data
after waiting one serial clock after the last bit of the 8-bit control message has been sent. The
returned data can be 4-16 bits in length making the total frame length in the range of 13-25
bits.
Texas Instruments synchronous serial frame format
Figure 57 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPTXD/
SSPRXD
nSSPOE
Figure 57.
In this mode, SSPCLKOUT and SSPFSSOUT are forced LOW and the transmit data line SSPTXD is
tristated whenever the PrimeCell SSP is idle. When the bottom entry of the transmit FIFO
contains data, SSPFSSOUT is pulsed HIGH for one SSPCLKOUT period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of SSPCLKOUT, the MSB of the 4-bit to 16-bit data frame
is shifted out on the SSPTXD pin. In a similar way, the MSB of the received data is shifted onto
the SSPRXD pin by the off-chip serial slave device.
Both the PrimeCell SSP and the off-chip serial slave device then clock each data bit into their
serial shifter on the falling edge of each SSPCLKOUT. The received data is transferred from the
serial shifter to the receive FIFO on the first rising edge of PCLK after the LSB has been latched.
W7500x Reference Manual Version1.1.0
MSB
Texas Instruments synchronous serial frame format, single transfer
4 to 16 bits
LSB
369 / 399
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