Table of Contents
Advertisement
17.3
Functional description ................................................................... 150
17.4
Registers (Base address : 0x4100_3000) ............................................... 152
PAD Control register (Px_y PCR)(x=A..D, y=0..15) ........................................ 152
17.5
Register map ............................................................................... 152
18 General-purpose I/Os(GPIO) ....................................................................... 153
18.1
Introduction ................................................................................ 153
18.2
Features .................................................................................... 153
18.3
Functional description ................................................................... 153
Masked access ................................................................................... 154
18.4
GPIO Registers(Address Base: 0x4200_0000) ......................................... 156
GPIO Data Register(GPIOx_DATA) (x=A..D) ................................................. 156
GPIO Output Latch Register(GPIOx_DATAOUT) (x=A..D) .................................. 156
GPIO Enable Set Register(GPIOx_OUTENSET) (x=A..D) ................................... 156
GPIO Enable Clear Register(GPIOx_OUTENCLR) (x=A..D) ................................ 157
GPIO Interrupt Enable Set Register(GPIOx_ INTENSET) (x=A..D) ....................... 157
GPIO Interrupt Enable Clear Register(GPIOx_ INTENCLR) (x=A..D)..................... 158
GPIO Interrupt Type Set Register(GPIOx_ INTTYPESET) (x=A..D) ....................... 158
GPIO Interrupt Type Clear Register(GPIOx_ INTTYPECLR) (x=A..D) .................... 159
GPIO Interrupt Polarity Set Register(GPIOx_ INTPOLSET) (x=A..D) ..................... 159
GPIO Interrupt Polarity Clear Register(GPIOx_ INTPOLCLR) (x=A..D) .................. 160
GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (x=A..D) ........ 161
GPIO Lower Byte Masked Access Register(GPIOx_ LB_MASKED) (x=A..D) .............. 161
GPIO Upper Byte Masked Access Register(GPIOx_ UB_MASKED) (x=A..D) ............. 162
18.5
Register map ............................................................................... 163
19 Direct memory access controller (DMA) ........................................................ 164
19.1
Introduction ................................................................................ 164
19.2
Features .................................................................................... 164
19.3
Functional description ................................................................... 164
DMA request mapping .......................................................................... 165
DMA arbitration .................................................................................. 165
DMA cycle types ................................................................................. 165
19.4
Registers (Base address : 0x4100_4000) ............................................... 168
DMA status register (DMA_STATUS) ........................................................... 168
DMA configuration register (DMA_CFG) ..................................................... 169
DMA control data base pointer register (DMA_CTRL_BASE_PTR) ....................... 170
(DMA_ALT_CTRL_BASE_PTR) .......................................................................... 170
DMA channel wait on request status register (DMA_WAITONREQ_STATUS) ............ 171
DMA channel software request register (DMA_CHNL_SW_REQUEST) ................... 171
W7500x Reference Manual Version1.1.0
8 / 399
Advertisement
Table of Contents
