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returned data is 4 to 16 bits in length, making the total frame length in the range of 13-25
bits.
In this configuration, during idle periods:
• SSPCLKOUT is forced LOW
• SSPFSSOUT is forced HIGH
• the transmit data line, SSPTXD, is arbitrarily forced LOW
• the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance.
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of
SSPFSSOUT causes the value contained in the bottom entry of the transmit FIFO to be
transferred to the serial shift register of the transmit logic and the MSB of the 8-bit control
frame to be shifted out onto the SSPTXD pin. SSPFSSOUT remains LOW for the duration of the
frame transmission. The SSPRXD pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge
of each SSPCLKOUT. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state and the slave responds by transmitting data back to the
PrimeCell SSP. Each bit is driven onto the SSPRXD line on the falling edge of SSPCLKOUT. The
PrimeCell SSP in turn latches each bit on the rising edge of SSPCLKOUT. At the end of the frame
for single transfers, the SSPFSSOUT signal is pulled HIGH one clock period after the last bit has
been latched in the receive serial shifter, which causes the data to be transferred to the
receive FIFO.
The off-chip slave device can tristate the receive line either on the falling edge of SSPCLKOUT
after the LSB has been latched by the receive shifter or when the SSPFSSOUT pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a single
transfer. However, the SSPFSSOUT line is continuously asserted, held LOW, and transmission of
data occurs back-to-back. The control byte of the next frame follows directly after the LSB of
the received data from the current frame. Each of the received values is transferred from the
receive shifter on the falling edge SSPCLKOUT, after the LSB of the frame has been latched
into the PrimeCell SSP.
Figure 66 shows the National Semiconductor Microwire frame format when back-to-back
frames are transmitted.
377 / 399
W7500x Reference Manual Version1.1.0
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