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Uartclk Prescale Value Select Register (Uartclk_Pvsr); Miiclk Enable Control Register (Miiclk_Ecr) - Wiznet W7500 Reference Manual

W7500 series

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UARTCLK prescale value select register (UARTCLK_PVSR)

Address offset : 0x154

Reset value : 0x0000_0000

[1:0] UCP – select prescale value of UARTCLK clock

These bits are written by S/W to select

00 : 1/1 (bypass)

Address offset : 0x160

Reset value : 0x0000_0003

[0] MIIREN – MII RX Clock source enable register

This bit is written by S/W to set enable or disable

0 : Disable MII_RCK and MII_RCK_N

1 : Enable MII_RCK and MII_RCK_N

[1] MIITEN – MII TX Clock source enable register

This bit is written by S/W to set enable or disable

0 : Disable MII_TCK and MII_TCK_N

1 : Enable MII_TCK and MII_TCK_N

W7500x Reference Manual Version1.1.0