Wiznet W7500 Reference Manual page 350

The UART1IMSC register is the interrupt mask set/clear interrupts. When a bit of UART1IMSC
is '1' and the corresponding bit of interrupt register is '1', an interrupt will be issued.
In other words, if a bit of UART1IMSC is '0', an interrupt will not be issued even if the
corresponding bit of interrupt register is '1'.
31 30 29 28 27
res res res res res
15 14 13 12
res Res res res
[10] OEIM – Overrun error interrupt mask
0: Disable UART1OEINTR
1: Enable UART1OEINTR
[9] BEIM – Break error interrupt mask
0: Disable UART1BEINTR
1: Enable UART1BEINTR
[8] PEIM – Parity error interrupt mask
0: Disable UART1EINTR
1: Enable UART1EINTR
[7] FEIM – Framing error interrupt mask
0: Disable UART1FEINTR
1: Enable UART1FEINTR
[6] RTIM – Receive timeout interrupt mask
0: Disable UART1RTINTR
1: Enable UART1RTINTR
[5] TXIM – Transmit interrupt mask
0: Disable UART1TXINTR
1: Enable UART1TXINTR
[4] RXIM – Receive interrupt mask
0: Disable UART1RXINTR
1: Enable UART1RXINTR
[3] DSRMIM – nUART1DSR modem interrupt mask
0: Disable UART1DSRINTR
1: Enable UART1DSRINTR
[2] DCDMIM – nUART1DCD modem interrupt mask
0: Disable UART1DCDINTR
W7500x Reference Manual Version1.1.0
26 25 24 23
res res res res
11 10 9 8
res
OEIM BEIM PEIM
R/W R/W R/W
22 21 20 19
res res res res
7 6 5 4
FEIM RTIM TXIM RXIM
R/W R/W R/W R/W
18 17 16
res res res
3 2 1 0
DSR DCD CTS RIMI
MIM MIM MIM M
R/W R/W R/W R/W
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