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In this mode, the controller can be configured to use either the primary or the alternate
channel control data structure. After the channel is enabled and the controller receives a
request for this channel, the flow for the auto-request cycle is as below:
The controller performs 2
1.
zero the flow continues at step 3.
2.
The controller arbitrates if there are any transfers remaining after 2
transfers. If the current channel c has the highest priority, the cycle continues
at step 1.
The controller sets dma_done[c] signal for this channel HIGH for one system clock cycle. This
indicates to the host processor that the DMA cycle is complete.
Ping-pong cycle
In this mode, the controller performs a DMA cycle using one of the data structures and then
performs a DMA cycle using the other data structure. The controller continues to switch
between primary and alternate structures until it reads a data structure that is invalid, until
the user reprograms the cycle_type to basic, or until the host processor disables the channel.
In ping-pong mode, the user can program or reprogram one of the two channel data structures
(primary or alternate) while using the other channel data structure for the active transfer.
When a transfer is done, the next transfer can be started immediately using the prepared
channel data structure – provided that a higher priority channel does not require servicing. If
the user does not reprogram the channel control data structure not in use for a transfer, the
cycle type remains invalid (which is the value at the end of the last transfer using that
structure), and the ping-pong cycle completes.
The ping-pong cycle can be used for transfers to or from peripherals or for memory- to-memory
transfers.
W7500x Reference Manual Version1.1.0
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transfers. If the number of transfers remaining is
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