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22.7 Register map
The following Table 27 summarizes the Dual timer 0_1 registers.
Table 27 Dual timer 0_1 register map and reset values
Offset
Register
DUALTIMER0_1TimerLoad
0x00
0
0
reset value
DUALTIMER0_1TimerValue
0x04
reset value
1
1
DUALTIMER0_1TimerControl
0x08
reset value
DUALTIMER0_1TimerIntClr
0x0C
reset value
DUALTIMER0_1TimerRIS
0x10
reset value
DUALTIMER0_1TimerMIS
0x14
reset value
DUALTIMER0_1TimerBGLoad
0x18
0
0
reset value
W7500x Reference Manual Version1.1.0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TLR
0
0
0
0
0
0
0
0
0
0
0
0
TVR
1
1
1
1
1
1
1
1
1
1
1
1
0
0
BGL
0
0
0
0
0
0
0
0
0
0
0
0
비고
Timer0_1 Load Register
0
0
0
0
0
0
Timer0_1 Value Register
1
1
1
1
1
1
Timer0_1 Control Register
1
0
0
0
0
Timer0_1 Interrupt Clear
Register
Write only register
Timer0_1 Raw Interrupt Status
Register
0
Timer0_1 Masked Interrupt
Status Register
0
Timer0_1 Background Load
Register
0
0
0
0
0
0
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