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22.11
Register map
The following Table 29 summarizes the Dual timer 1_0 registers.
Table 29 Dual timer 1_0 register map and reset values
Offset
Register
DUALTIMER1_0TimerLoad
0x00
0
0
reset value
DUALTIMER1_0TimerValue
0x04
reset value
1
1
DUALTIMER1_0TimerControl
0x08
reset value
DUALTIMER1_0TimerIntClr
0x0C
reset value
DUALTIMER1_0TimerRIS
0x10
reset value
DUALTIMER1_0TimerMIS
0x14
reset value
DUALTIMER1_0TimerBGLoad
0x18
0
0
reset value
W7500x Reference Manual Version1.1.0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TLR
0
0
0
0
0
0
0
0
0
0
0
0
TVR
1
1
1
1
1
1
1
1
1
1
1
1
0
0
BGL
0
0
0
0
0
0
0
0
0
0
0
0
비고
Timer1_0 Load Register
0
0
0
0
0
0
Timer1_0 Value Register
1
1
1
1
1
1
Timer1_0 Control Register
1
0
0
0
0
Timer1_0 Interrupt Clear
Register
Write only register
Timer1_0 Raw Interrupt Status
Register
0
Timer1_0 Masked Interrupt
Status Register
0
Timer1_0 Background Load
Register
0
0
0
0
0
0
295 / 399
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