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F
(min) => 12 x F
SSPCLK
The maximum frequency of SSPCLK is calculated by the following equations, both of which
must be satisfied:
F
(max) <= 254 x 256 x F
SSPCLK
F
(max) <= 254 x 256 x F
SSPCLK
Programming the SSPCR0 Control Register
The SSPCR0 register is used to:
• program the serial clock rate
• select one of the three protocols
• select the data word size, where applicable.
The Serial Clock Rate (SCR) value in conjunction with the SSPCPSR clock prescale divisor value,
CPSDVSR, is used to derive the PrimeCell SSP transmit and receive bit rate from the external
SSPCLK.
The frame format is programmed through the FRF bits and the data word size through the DSS
bits.
Bit phase and polarity applicable to Motorola SPI format only are programmed through the SPH
and SPO bits.
Programming the SSPCR1 Control Register
The SSPCR1 register is used to:
• select master or slave mode
• enable a loop back test feature
• enable the PrimeCell SSP peripheral.
To configure the PrimeCell SSP as a master, clear the SSPCR1 register master or slave selection
bit, MS, to 0. This is the default value on reset.
Setting the SSPCR1 register MS bit to 1 configures the PrimeCell SSP as a slave. When
configured as a slave, enabling or disabling of the PrimeCell SSP SSPTXD signal is provided
through the SSPCR1 slave mode SSPTXD output disable bit, SOD. You can use this in some multi-
slave environments where masters might parallel broadcast.
W7500x Reference Manual Version1.1.0
(max), for slave mode.
SSPCLKIN
(min), for master mode
SSPCLKOUT
(min), for slave mode.
SSPCLKIN
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