Rtc Clock; Rtc Interrupt; Rtc Counter And Calendar - Wiznet W7500 Reference Manual

RTCCLK 1Hz Clock
Divider
DIVRST
BCD
Consolidated
BCD

RTC clock

RTC Clock (RTCCLK) can be selected among several clocks (32768Hz oscillator, MCLK,
RCLK, OCLK). Please refer to the Clock Reset Generator chapter for configuring the clock.
If the 32768Hz oscillator clock is used, the divider generates 1 Hz clock internally.
If the DIVRST (Bit[1] of RTC Control Register ) value is high, the RTC Divider is cleared. If
the DIVRST value is low, the divider operates.

RTC interrupt

RTC has two kinds of interrupt source, Counter Interrupt and Alarm Interrupt.
Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
There are following Counter Interrupts: Second, Minute, Hour, Day (Day of Week), Date
(Day of Month) and Year.
Each bit of RTCINTM (Interrupt Mask Register) can disable or enable interrupt for each
Counter Interrupt.
Alarm Interrupt can be generated when the Alarm matches with Counter.

RTC Counter and Calendar

When user writes 1 to bit 0 of control register, then the RTC counter runs according to
the RTC Clock.
Timer value should be written as the BCD format.
The RTC counter operates for Calendar function including Day, Month, Year and Leap Year
calculation.
W7500x Reference Manual Version1.1.0
RTC BCD Counter
Counter
Increment
...
Match
=
...
PreBCD
Figure 42. RTC block diagram
Counter
Counter
Interrupt
Interrupt
Pending
clear
Alarm
Interrupt
Alarm
INTEN
Interrupt
Pending
clear
RTC
interrupt
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