Adc Interrupt Clear Register (Adc_Intclr) - Wiznet W7500 Reference Manual

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[0] DONE – Interrupt bit
This bit indicates that conversion is done or not. This bit is set after conversion is done
and this bit is cleared by set of Interrupt clear bit. This bit is read-only.
[1] MASK – Interrupt mask signal.
This bit is interrupt mask bit of ADC. This bit can be set and cleared by S/W to
enable/disable interrupt mask.
0 : Interrupt disable
1 : Interrupt enable

ADC Interrupt Clear register (ADC_INTCLR)

Address offset : 0x01c
Reset value : 0x0000_0000
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[0] INTCLR – Interrupt Clear bit.
This bit set by S/W to clear interrupt signal to CM0. This bit is write-only.
0 – nothing
1 – Clear interrupt signal (This bit clear automatically after clear interrupt)
W7500x Reference Manual Version1.1.0
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res res MASK INT
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