Uart2 Registers(Base Address: 0X4000_6000); Uart2Dr (Uart2 Data Register); Uart2Sr (Uart2 Status Register) - Wiznet W7500 Reference Manual

26.4 UART2 Registers(Base address: 0x4000_6000)

UART2DR (UART2 Data Register)

Address offset: 0x000
Reset value: 0x0000_0000
The UART2DR is the data register.
The write operation initiates transmission from the UART2. The received data byte is read by
performing reads from the UART2DR register along with the corresponding status information.
31 30 29 28
res res res res
15 14 13 12
res res res res
[7:0] DATA – Receive (READ)/Transmit (WRITE) data

UART2SR (UART2 Status Register)

Address offset: 0x004
Reset value: 0x0000_0000
The UART2SR is the status register. RXBF and TXBF is read only.
A write to the UART2SR register clears the TX/RX overrun errors.
31 30 29 28
res res res res
15 14 13 12
res res res res
[3] RXO –Receive Overrun
[2] TXO – Transmit Overrun
[1] RXBF – Receive buffer full
Read Only
0: The bit is set when the receive holding register is full
1: The bit is set when the receive buffer is full
[0] TXBF – Transmit buffer full
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
DATA
23 22 21 20
res res res res
7 6 5 4
res res res res
19 18 17
res res res
3 2 1
R/W
19 18 17
res res res
3 2 1
RXO TXO RXBF
R/W R/W R
357 / 399
16
res
0
16
res
0
TXBF
R