Ssp0 Status Register (Ssp0Sr) - Wiznet W7500 Reference Manual

15 14 13 12
[15:0] DATA – Transmit/Receive FIFO:
Read: Read: receive FIFO.
Write: transmit FIFO.
You must right-justify data when the SSP0 is programmed for a data size that is less
than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic
automatically right-justifies.

SSP0 Status register (SSP0SR)

Address offset: 0x000C
Reset value: 0x0000_0003
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] TFE – Transmit FIFO empty, RO
0 : Transmit FIFO is not empty.
1 : Transmit FIFO is empty.
[1] TNF – Transmit FIFO not full, RO:
0 : Transmit FIFO is full.
1 : Transmit FIFO is not full.
[2] RNE – Receive FIFO not empty, RO:
0 : Receive FIFO is empty.
1 : Receive FIFO is not empty.
[3] RFF – Receive FIFO full, RO:
0 : Receive FIFO is not full.
1 : Receive FIFO is full.
[4] BSY – SSP busy flag, RO:
0 : SSP is idle.No effect
W7500x Reference Manual Version1.1.0
11 10 9 8
Data
27 26 25 24
res res res res
11 10 9 8
res res res res
7 6 5
R/W
23 22 21
res res res
7 6 5
res res res
4 3 2 1
20 19 18 17
res res res res
4 3 2 1
BSY RFF RNE TNF
R/W R/W R/W R/W
383 / 399
0
16
res
0
TFE
R/W