Channel-0 Interrupt Enable Register(Pwmch0Ier) - Wiznet W7500 Reference Manual

15 14 13 12
res res res res
[0] MI – Match Interrupt
This bit is set by hardware and cleared by interrupt clear register.
0 : Match interrupt does not occur.
1 : Match interrupt occurs.
[1] OI – Overflow Interrupt
This bit is set by hardware and cleared by interrupt clear register.
0 : Overflow interrupt does not occur.
1 : Overflow interrupt occurs.
[2] CI – Capture Interrupt
This bit is set by hardware and cleared by interrupt clear register.
0 : Capture interrupt does not occur.
1 : Capture interrupt occurs.

Channel-0 interrupt enable register(PWMCH0IER)

Base address : 0x4000_5000
Address offset : 0x04
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] MIE – Match Interrupt Enabled.
0 : Match interrupt is not enabled.
1 : Match interrupt is enabled.
[1] OIE – Overflow Interrupt Enable.
0 : Overflow interrupt is not enabled.
1 : Overflow interrupt is enabled.
[2] CIE – Capture Interrupt Enable.
0 : Capture interrupt is not enabled.
1 : Capture interrupt is enabled.
W7500x Reference Manual Version1.1.0
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res res
7 6 5 4
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
3 2 1 0
res CI OI MI
R R R
19 18 17 16
res res res res
3 2 1 0
res CIE OIE MIE
R/W R/W R/W
199 / 399