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22.5 Register map
The following Table 26 summarizes the Dual timer 0_0 registers.
Table 26 Dual timer 0_0 register map and reset values
Offset
Register
DUALTIMER0_0TimerLoad
0x00
0
0
reset value
DUALTIMER0_0TimerValue
0x04
1
1
reset value
DUALTIMER0_0TimerControl
0x08
reset value
DUALTIMER0_0TimerIntClr
0x0C
reset value
DUALTIMER0_0TimerRIS
0x10
reset value
DUALTIMER0_0TimerMIS
0x14
reset value
DUALTIMER0_0TimerBGLoad
0x18
0
0
reset value
W7500x Reference Manual Version1.1.0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TLR
0
0
0
0
0
0
0
0
0
0
0
0
TVR
1
1
1
1
1
1
1
1
1
1
1
1
0
0
BGL
0
0
0
0
0
0
0
0
0
0
0
0
비고
Timer0_0 Load Register
0
0
0
0
0
0
Timer0_0 Value Register
1
1
1
1
1
1
Timer0_0 Control Register
1
0
0
0
0
Timer0_0 Interrupt Clear
Register
Write only register
Timer0_0 Raw Interrupt Status
Register
0
Timer0_0 Masked Interrupt
Status Register
0
Timer0_0 Background Load
Register
0
0
0
0
0
0
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