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Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) ................... 293
22.11
Register map ............................................................................... 295
22.12
Dual timer1_1 Registers (Base address : 0x4000_2020) ............................ 296
Timer1_1 Load Register(DUALTIMER1_1TimerLoad) ....................................... 296
Timer1_1 Value Register(DUALTIMER1_1TimerValue) ..................................... 296
Timer1_1 Control Register(DUALTIMER1_1TimerControl) ................................ 296
Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr) ........................ 297
Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) .................... 297
Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) ................ 298
Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad) ................... 298
22.13
Register map ............................................................................... 300
22.14
Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) .............. 301
Timer1_0 Clock Enable Register (TIMCLKEN1_0) .......................................... 301
Timer1_1 Clock Enable Register (TIMCLKEN1_1) .......................................... 301
22.15
Register map ............................................................................... 302
23 Watchdog timer ...................................................................................... 302
23.1
Introduction ................................................................................ 302
23.2
Features .................................................................................... 302
23.3
Functional description ................................................................... 302
Clock........ ...................................................................................... 302
Interrupt and reset request ................................................................... 303
23.4
Watchdog timer Registers (Base address : 0x4000_0000) .......................... 303
Watchdog timer Load Register(WDTLoad) .................................................. 303
Watchdog timer Value Register(WDTValue) ................................................ 304
Watchdog timer Control Register(WDTControl) ............................................ 304
Watchdog timer Interrupt Clear Register (WDTIntClr) .................................... 304
Watchdog timer Raw Interrupt Status Register (WDTRIS) ................................ 305
Watchdog timer Masked Interrupt Status Register (WDTMIS) ........................... 305
Watchdog timer Lock Register(WDTLock) ................................................... 306
23.5
Register map ............................................................................... 307
24 Real-time Clock(RTC) ............................................................................... 307
24.1
Introduction ................................................................................ 307
24.2
Features .................................................................................... 307
24.3
Functional description ................................................................... 307
RTC clock.... ..................................................................................... 308
RTC interrupt .................................................................................... 308
RTC Counter and Calendar .................................................................... 308
RTC Setting flow ................................................................................ 309
24.4
RTC Registers (Base Address : 0x4000_E000) ......................................... 310
W7500x Reference Manual Version1.1.0
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