Channel-0 Interrupt Clear Register(Pwmch0Icr); Channel-0 Timer/Counter Register (Pwmch0Tcr) - Wiznet W7500 Reference Manual

Channel-0 interrupt clear register(PWMCH0ICR)

Base address : 0x4000_5000
Address offset : 0x08
31 30 29 28
res res res res
15 14 13 12
res res res res
This bit is set by software, cleared by hardware when a capture interrupt becomes 0.
[0] MIC – Match Interrupt
0 : No action.
1 : Match interrupt is cleared.
[1] OIC – Overflow Interrupt
0 : No action.
1 : Overflow Interrupt is cleared.
[2] CIC – Capture Interrupt Clear.
0 : No action.
1 : Capture Interrupt is cleared.

Channel-0 Timer/Counter Register (PWMCH0TCR)

Base address : 0x4000_5000
Address offset : 0x0C
Reset value : 0x0000_0000
31
[31:0] TCR – Timer/Counter register
Timer/Counter register. These register hold the current values of the
Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is
reached to value of match register, the match interrupt is occurred and PWM
output waveform becomes 0. When the TC is reached to the value of limit
register, the overflow interrupt is occurred, the TC is reset as 0.
W7500x Reference Manual Version1.1.0
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res res res res
11 10 9 8
res res res res
23 22 21
res res res
7 6 5
res res res
TCR
R
20 19 18 17
res res res res
4 3 2 1
res res CIC OIC
W W
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16
res
0
MIC
W
0