Uart1Ifls (Uart1 Interrupt Fifo Level Select Register); Uart1Imsc (Uart1 Interrupt Mask Set/Clear Register) - Wiznet W7500 Reference Manual

0: IrDA SIR ENDEC is disable
1: IrDA SIR ENDEC is enable
[0] UARTEN – UART enable
0: UART is disabled
1: UART is enabled
Program the control registers as follows:
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by setting the FEN bit to 0 in the Line Control Register,
UARTLCR_H on page 3-12.
4. Reprogram the UARTCR Register.
5. Enable the UART.

UART1IFLS (UART1 Interrupt FIFO Level Select Register)

Address offset: 0x0034
Reset value: 0x12
The UARTIFLS register is the interrupt FIFO level select register.
31 30 29 28
res res res res
15 14 13 12
res res res res
[5:3] RXIFLSEL – Receive interrupt FIFO level select
7 6
Reserved
[2:0] TXIFLSEL – Transmit interrupt FIFO level select
7 6
Reserved

UART1IMSC (UART1 Interrupt Mask Set/Clear Register)

Address offset: 0x0038
Reset value: 0x00
W7500x Reference Manual Version1.1.0
27 26 25
res res res
11 10 9
res res res
5 4
7/8 full 3/4 full
5 4
7/8 full 3/4 full
24 23 22 21
res res res res
8 7 6 5
res res res
3 2
1/2 full
3 2
1/2 full
20 19 18
res res res
4 3 2
RXIFLSEL TXIFLSEL
W
1 0
1/4 full 1/8 full
1 0
1/4 full 1/8 full
349 / 399
17 16
res res
1 0
W