Ssp0 Registers (Base Address : 0X4000_A000); Ssp0 Control Register 0 (Ssp0Cr0) - Wiznet W7500 Reference Manual

Figure 70 shows how to setting SPI mode.
SPI Data Send
(Master mode)
SerialClockRate
(choose 0~255)
Y
CPHA == 0 ?
Captured 1 Edge
Y
CPHA == 0 ?
Captured 1 Edge
(Slave Output
Disable) Setting
DataSize Setting
(choose 4~16bits)
(Syncronous
Serialport Enable)
BaudRatePrescaler

27.4 SSP0 Registers (Base Address : 0x4000_A000)

This section describes the SSP0 registers.

SSP0 Control register 0 (SSP0CR0)

Address offset: 0x0000
Reset value: 0x0000_0000
31 30 29 28
W7500x Reference Manual Version1.1.0
to Slave
Setting
N
Captured 2 Edge
N
Captured 2 Edge
SOD
SSE
Setting
Setting
(4~254)
End
Figure 70. how to setting SPI mode flow chart
27 26 25
Y
Captured 1 Edge
Y
Captured 1 Edge
Serialport Enable)
24 23 22 21
SPI Data Send
to Master
(Slave mode)
N
CPHA == 0 ?
Captured 2 Edge
N
CPHA == 0 ?
Captured 2 Edge
SOD
(Slave Output
Disable) Setting
Mode Setting
(choose Slave)
SSE
(Syncronous
Setting
End
20 19 18
380 / 399
17 16