Fclk Prescale Value Select Register (Fclk_Pvsr); Sspclk Source Select Register (Sspclk_Ssr) - Wiznet W7500 Reference Manual

00, 01 : output clock of PLL (MCLK)
10 : Internal 8MHz RC oscillator clock (RCLK)
11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

FCLK prescale value select register (FCLK_PVSR)

Address offset : 0x034
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
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[1:0] FCKPRE – select prescale value of FCLK clock
These bits are written by S/W to select
00 : 1/1 (bypass)
01 : 1/2
10 : 1/4
11 : 1/8

SSPCLK source select register (SSPCLK_SSR)

Address offset : 0x040
Reset value : 0x0000_0001
31 30 29 28
res res res res
15 14 13 12
res res res res
[1:0] SSPCSS – SSPCLK clock source select register.
These bits are written by S/W to select clock source
00 : disable clock
01 : PLL output clock (MCLK)
10 : Internal 8MHz RC oscillator clock (RCLK)
11 : External oscillator clock (OCLK, 8MHz ~ 24MHz)
W7500x Reference Manual Version1.1.0
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R/W
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