Gpio Interrupt Status/Clear Register(Gpio_ Intstatus/Intclear) (X=A; Gpio Lower Byte Masked Access Register(Gpiox_ Lb_Masked) (X=A - Wiznet W7500 Reference Manual

GPIO Interrupt Status/Interrupt Clear Register(GPIO_ INTSTATUS/
INTCLEAR) (x=A..D)
Address offset: 0x0038
Reset value: 0x----
31 30 29
res res res
15 14 13
ISC15 ISC14 ISC13
R/W R/W R/W
[15:0] ISCy(y = 0..15)
WRITE as :
'0' is no effect
'1' is request to clear the interrupt
READ as : IRQ status Register
GPIO Lower Byte Masked Access Register(GPIOx_ LB_MASKED)
(x=A..D)
Address offset: 0x0400 – 0x07FC
Reset value: 0x----
31 30 29 28
res res res res
15 14 13 12
res res res res
R/W R/W R/W R/W
Lower eight bits masked access
[15:8] Not used
[7:0] Data for lower byte access, with bits[9:2] of address value used as enable bit mask for
each bit
W7500x Reference Manual Version1.1.0
28 27 26 25
res res res res
12 11 10 9
ISC12 ISC11 ISC10 ISC9
R/W R/W R/W R/W
27 26 25
res res res
11 10 9
res res res
R/W R/W R/W
24 23 22 21
res res res res
8 7 6 5
ISC8 ISC7 ISC6 ISC5
R/W R/W R/W R/W
24 23 22 21
res res res res
8 7 6
res
R/W R/W R/W R/W
20 19 18
res res res
4 3 2
ISC4 ISC3 ISC2
R/W R/W R/W
20 19 18
res res res
5 4 3 2
LBM
R/W R/W R/W
161 / 399
17 16
res res
1 0
ISC1 ISC0
R/W R/W
17 16
res res
1 0
R/W R/W