Channel-0 Limit Register (Pwmch0Lr); Channel-0 Up-Down Mode Register (Pwmch0Udmr) - Wiznet W7500 Reference Manual

31
[31:0] MR – Match Register
Match register. The MR can generate a match interrupt and PWM output
waveform becomes 0 when the TC is reached to the MR. Match register should
be smaller than limit register(LR). If not, match interrupt is not occurred and
PWM output waveform is always 1.

Channel-0 Limit Register (PWMCH0LR)

Base address : 0x4000_5000
Address offset : 0x1C
Reset value : 0x0000_0000
31
[31:0] LR – Limit Register
Limit Register. The LR can generate an overflow interrupt and PWM output
waveform becomes 1 when the TC is reached to the LR. Match register should
be smaller than limit register(LR). If not, match interrupt is not occurred and
PWM output waveform is always 1.

Channel-0 Up-Down Mode Register (PWMCH0UDMR)

Base address : 0x4000_5000
Address offset : 0x20
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] UDM – Up-Down mode
0 : TC runs up count.
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
MR
R/W
LR
R/W
23 22 21
res res res
7 6 5
res res res
20 19 18 17
res res res res
4 3 2 1
res res res res
202 / 399
0
0
16
res
0
UDM
R/W