Channel-5 Timer/Counter Mode Register (Pwmch5Tcmr); Channel-5 Pwm Output Enable And External Input Enable Register (Pwmch5Peeer) - Wiznet W7500 Reference Manual

Address offset : 0x20
Reset value : 0x0000_0000
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15 14 13 12
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[0] UDM – Up-Down mode
0 : TC runs up count.
1 : TC runs down count.

Channel-5 Timer/Counter Mode Register (PWMCH5TCMR)

Base address : 0x4000_5500
Address offset : 0x24
Reset value : 0x0000_0000
31 30 29 28
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15 14 13 12
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[1:0] TCM – Timer/Counter mode
00 : Timer mode.
01 : Counter mode with counting driven by rising edge external input .
10 : Counter mode with counting driven by falling edge external input.
11 : Counter mode with counting driven by rising and falling edge external
Channel-5 PWM output Enable and External input Enable
Register (PWMCH5PEEER)
Base address : 0x4000_5500
Address offset : 0x28
Reset value : 0x0000_0000
W7500x Reference Manual Version1.1.0
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input.
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3 2 1 0
res res res UDM
R/W
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3 2 1 0
res res TCM
R/W
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