Sending Side Program For Cpu No.1; Receiving Side Program For Cpu No.2 (C Controller Module); Interlock Program Example - Mitsubishi Electric Q12DCCPU-V User Manual

13
COMMUNICATIONS BETWEEN CPU MODULES

Sending side program for CPU No.1

(programmable controller CPU)
Write
command
M100 M0 M3
6)
M0 M3
13
- 22 13.3 Data Communications Using CPU Shared Memory
13.3.2 Data communications using auto refresh
{
unsigned short
1)
unsigned short
Set send data in
D0 to D9.
/***********************************************************************/
/* Confirm that 1 is set in the area corresponding to M0 in the CPU No.1 auto refresh area. */
2)
/* (CPU No.1 data set completion bit turns ON.)
SET M0
/***********************************************************************/
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 0x800, 1, &usBuf, 1);
RST M0
if( sRet != 0) return(sRet);
if( (usBuf & 0x1) == 0x1 ) break;
RST M100
taskDelay(2);
}
/****************************************************************/
/* Data are read from the area corresponding to D0 to D9 in the CPU No.1 auto refresh area. */
/****************************************************************/
sRet = QBF_FromBuf(lPath, 0x3E0, 0x802, 10, pusData, 128);
if( sRet != 0) return(sRet);
/*****************************************************************/
/* 1 is set in the host CPU's auto refresh area corresponding to M32 of CPU No.1. */
/* (CPU No.2 data processing completion bit turns ON.) */
/*****************************************************************/
usBuf = 1;
sRet = QBF_ToBuf(lPath, 0x3E1, 0x800, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
/***********************************************************************/
/* Confirm that 0 is set in the area corresponding to M0 in the CPU No.1 auto refresh area. */
/* (CPU No.1 data set completion bit turns OFF.)
/***********************************************************************/
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 0x800, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
if( (usBuf & 0x1) == 0x0 ) break;
taskDelay(2);
}
/*****************************************************************/
/* 0 is set in the host CPU's auto refresh area corresponding to M32 of CPU No.1. */
/* (CPU No.2 data processing completion bit turns OFF.) */
/*****************************************************************/
usBuf = 0;
sRet = QBF_ToBuf(lPath, 0x3E1, 0x800, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
}
Figure 13.15 Interlock program example

Receiving side program for CPU No.2 (C Controller module)

:
usBuf; /* Data storage destination */
pusData[128]; /* Data storage destination */
:
/* When 1 is set, processing gets out from the loop. */
/* When 0 is set, processing gets out from the loop. */
*/
3)
4)
5)
*/
7)
8)