Mitsubishi Electric Q12DCCPU-V User Manual page 432

13
COMMUNICATIONS BETWEEN CPU MODULES
13
- 34 13.3 Data Communications Using CPU Shared Memory
13.3.4 Data communications without using auto refresh
1) CPU No.1 writes send data to the user setting area.
2) CPU No.1 writes the data set completion bit ON to the user setting area.
The multiple CPU high speed transmission area data of CPU No.1 are sent to
CPU No.2.
3) CPU No.2 detects ON of the data set completion bit.
4) CPU No.2 processes the received data.
5) CPU No.2 writes the data processing completion bit ON to the user setting
area.
The multiple CPU high speed transmission area data of CPU No.2 are sent to
CPU No.1.
6) CPU No.1 detects ON of the data processing completion bit, and turns OFF
the data set completion bit.
The multiple CPU high speed transmission area data of CPU No.1 are sent to
CPU No.2.
7) CPU No.2 detects OFF of the data set completion bit.
8) CPU No.2 writes the data processing completion bit OFF to the user setting
area.