Mitsubishi Electric Q12DCCPU-V User Manual page 431

13
COMMUNICATIONS BETWEEN CPU MODULES
Sending side program for CPU No.1 (programmable
controller CPU)
Write
U3E0\ U3E1\
command
M0 G10010.0 G10000.0
1)
Set send data in
user setting area
(U3E0\ G10000 to G10009).
6)
U3E0\ U3E1\
G10010.0 G10000.0
<Interlock program example>
Depending on the following timing, old and new data for each CPU may be mixed
(data separation).
• Writing data to the user setting area in another CPU and reading another
CPU's user setting area data from the host CPU
• Writing data to the user setting area in the host CPU and reading host CPU's
user setting area data from another CPU
The following explains how to avoid data separation in data communications
through user setting areas.
Figure 13.23 shows an example, in which an interlock is programmed for sending
data from CPU No.1 (programmable controller CPU) to CPU No.2 (C Controller
module) using user setting areas in the multiple CPU high speed transmission
areas.
{
unsigned short
unsigned short
/****************************************************************/
U3E0\ /* The ON status of CPU No.1 data set completion bit is detected.*/
2)
/****************************************************************/
SET G10010.0
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 10010, 1, &usBuf, 1);
U3E0\
if( sRet != 0) return(sRet);
RST G10010.0
if( (usBuf & 0x1) == 0x1 ) break;
taskDelay(2);
RST M0 }
/****************************************************************/
/* Data are read out from the CPU No.1 user setting area.
/****************************************************************/
sRet = QBF_FromBuf(lPath, 0x3E0, 10000, 10, pusData, 128);
if( sRet != 0) return(sRet);
/*****************************************************************/
/* CPU No.2 data processing completion bit turns ON.
/*****************************************************************/
usBuf = 1;
sRet = QBF_ToBuf(lPath, 0x3E1, 10000, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
/*****************************************************************/
/* The OFF status of CPU No.1 data set completion bit is detected.*/
/*****************************************************************/
while(1){
sRet = QBF_FromBuf(lPath, 0x3E0, 10010, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
if( (usBuf & 0x1) == 0x0 ) break;
taskDelay(2);
}
/*****************************************************************/
/* CPU No.2 data processing completion bit turns OFF. */
/*****************************************************************/
usBuf = 0;
sRet = QBF_ToBuf(lPath, 0x3E1, 10000, 1, &usBuf, 1);
if( sRet != 0) return(sRet);
}
Figure 13.23 Interlock program example
13.3 Data Communications Using CPU Shared Memory
13.3.4 Data communications without using auto refresh
Receiving side program for CPU No.2 (C Controller module)
:
usBuf; /* Data storage destination */
pusData[128]; /* Data storage destination */
:
/* When 1 is set, processing gets out from the loop. */
/* When 0 is set, processing gets out from the loop. */
3)
*/
4)
*/
5)
7)
8)
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