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6 B
CHAPTER
Input
K00–K03
K10–K13
P00 (SIN)
I/O
P01 (SOUT)
P02 (SCLK)
P03 (SRDY)
P10–P13
R00
Output
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
R
A1
BZ
Piezo
BZ
R
A2
CMPP0
CMPM0
X'tal
C
GX
CR
C
GC
C
DC
R
CR
C
–C
1
8
C
P
C
RES
R
, R
A1
A2
Note: The above table is simply an example, and is not guaranteed to work.
S1C63666 TECHNICAL MANUAL
E
ASIC
XTERNAL
LCD panel
S1C63666
[The potential of the substrate
(back of the chip) is V
Crystal oscillator
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation
Capacitor
Capacitor
RESET terminal capacitor
Protective resistor
CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM
W
IRING
64 × 8
SVD
CA
CB
CC
CD
RESET
V
DDA
V
DD
V
D1
V
D2
V
OSC
.]
SS
OSC1
OSC2
OSC3
OSC4
TEST
V
SSA
V
SS
32.768 kHz, C
(Max.) = 34 kΩ
I
5–25 pF
4 MHz (3.0 V)
30 pF
30 pF
30 kΩ (2 MHz)
0.2 µF
3.3 µF
0.1 µF
100 Ω
EPSON
D
IAGRAM
C
1
C
2
C
RES
+
C
P
C
3
C
4
C
5
C
GX
X'tal
C
GC
CR
C
DC
∗1
∗2
∗1: Ceramic oscillation
∗2: CR oscillation (external R)
2.4 V
|
3.6 V
141
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