Debug Control Register; Figure 9-15 Debug Control Register Format; Table 9-9 Debug Control Register Bit Assignments - Epson ARM720T Core Cpu Manual

9.24

Debug control register

The Debug Control Register is six bits wide. Writes to the Debug Control Register occur when
a watchpoint unit register is written. Reads of the Debug Control Register occur when a
watchpoint unit register is read. See
information.
Figure 9-15 shows the function of each bit in the Debug Control Register.
5
EmbeddedICE-RT
disable
The Debug Control Register bit assignments are shown in Table 9-9.
Bit
5
4
3
2
1
0
ARM720T CORE CPU MANUAL
Watchpoint unit registers
4
Monitor mode
enable

Figure 9-15 Debug control register format

Table 9-9 Debug control register bit assignments

Function
Used to disable the EmbeddedICE-RT comparator outputs while
the watchpoint and breakpoint registers are being programmed.
This bit can be read and written through JTAG.
Set bit 5 when:
• programming breakpoint or watchpoint registers
• changing bit 4 of the Debug Control Register.
You must clear bit 5 after you have made the changes, to
re-enable the EmbeddedICE-RT logic and make the new
breakpoints and watchpoints operational.
Used to determine the behavior of the core when breakpoints or
watchpoints are reached:
• If clear, the core enters debug state when a breakpoint
or watchpoint is reached.
• If set, the core performs an abort exception when a
breakpoint or watchpoint is reached.
This bit can be read and written from JTAG.
This bit must be clear.
Used to disable interrupts:
• If set, the interrupt enable signal of the core (IFEN) is
forced LOW. The IFEN signal is driven as shown in
Table 9-10.
• If clear, interrupts are enabled.
Used to force the value on DBGRQ.
Used to force the value on DBGACK.
EPSON
on page 9-33 for more
3 2
SBZ/RAZ INTDIS DBGRQ
9: Debugging Your System
1 0
DBGACK
9-39