System Clock Timing (12.288 Mhz) - Epson S1V3G340 Hardware Specification

90% VIH
10% VIL
Symbol
f
OSC
T
OSC
t
pwh
t
pw
ｌ
t
r
t
f
t
CJper
t
CJcycle
*1
*2
*3
*4
*
S1V3G340 Hardware Specification
(Rev. 1.0)
Downloaded from Elcodis.com electronic components distributor
6.4.2

System Clock Timing (12.288 MHz)

t
PWH
1
1
t
r
t
t
CJper
Figure 6.2 System clock timing (12.288 MHz)
Parameter
Input clock frequency
Input clock period
Input clock pulse width high
Input clock pulse width low
Input clock rising time (10% → 90%)
Input clock falling time (90% → 10%)
Input clock period jitter (*2, 4)
Input clock cycle jitter (*1, 3, 4)
t = t – t
CJcycle cycle1 cycle2
The input clock period jitter is the displacement relative to the center period (reciprocal of center
frequency).
The input clock cycle jitter is difference in period between adjacent cycles.
The jitter characteristics must meet both t
Great care must be taken to ensure that overshooting or undershooting does not occur for the clock.
t
PWL
t
f
T
OSC
cycle1
0.45*T
0.45*T
and t characteristics.
Cjper CJcycle
EPSON
6. Electrical Characteristics
t
cycle2
Min. Typ. Max.
- 12.288 -
- 1/fosc -
- 0.55*T
osc
- 0.55*T
osc
- - 5.0
- - 5.0
-400 - 400
-400 - 400
Unit
MHz
μs
μs
osc
μs
osc
ns
ns
ps
ps
19