Figure 2.1.2K Generating A Physical Address In Direct Addressing Mode - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Program counter bank register (PCB) <Initial value: Value in reset vector>
Data bank register(DTB) <Initial value: 00H>
User stack bank register(USB) <Initial value: 00H>
System stack bank register(SSB) <Initial value: 00H>
Additional data bank register(ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other
than PCB can be read or written to. PCB can be read but cannot be written to.
PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the entire
16-Mbyte space is executed or when an interrupt occurs. For operation of each register, see Chapter 2,
Section 2.1.1, "Memory space."
Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in
Figure 2.1.2k. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by
an instruction.
DTB register
α α α α α α α α
24-bit physical
address

Figure 2.1.2k Generating a physical address in direct addressing mode

MB90580 Series
MSB
α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ
DPR register
β β β β β β β β
Direct address during instruction
γ γ γ γ γ γ γ γ
LSB
Chapter 2: CPU
2.1 CPU
27