Fig. 2.39 Shift Start/Stop Timing - Fujitsu MB89140 Series Hardware Manual

8-BIT SERIAL I/O
SCK
SST
IRQ
SO
[When transfer terminated]
SCK
SST
SIOF
SO
[When transfer suspended]
SCK
SST
SIOF
SO
[When transfer terminated]
SCK
SST
SIOF
SO
[When transfer suspended]
SCK
SST
SIOF
SO
HARDWARE CONFIGURATION
(3) Interrupt functions
This module can output an interrupt request to the CPU. To output an inter-
rupt request, set the SIOE bit of the SMR to 1 to enable an interrupt and then
set the interrupt flag SIOF bit of the SMR after 8-bit data transfer is termi-
nated.
#0 #1 #2 #3
(4) Shift start/stop timing
Data transfer starts when 1 is written at the SST bit of the SMR, and stops
when 0 is written. When data transfer is terminated, the SST bit is automati-
cally cleared to 0, which stops the operation.
Internal shift-clock mode (LSB first)
#0 #1 #2 #3
#0 #1 #2 #3
External shift-clock mode (LSB first)
#0 #1 #2 #3
#0 #1 #2 #3
Note: When data is written at the SDR, the output data changes at the
falling edge of the external-clock pulse.

Fig. 2.39 Shift Start/Stop Timing

2-74
#4 #5 #6 #7
#4 #5 #6 #7
#4 #5
#4 #5 #6 #7
#4 #5