Instruction Stream Timing Examples - Motorola MC68020 User Manual

8.1.5 Instruction Stream Timing Examples

A programming example allows a more detailed examination of these effects. The effect of
instruction execution overlap on instruction timing is illustrated by the following example
instruction stream.
Example 1
For the first example, the assumptions are:
1. The data bus is 32 bits,
2. The first instruction is prefetched from an odd-word address,
3. Memory access occurs with no wait states, and
4. The instruction cache is disabled.
For example 1, the instruction stream is positioned in 32-bit memory as follows:
Figure 8-3 shows processor activity on the first example instruction stream. It shows the
activity of the external bus, the bus controller, the sequencer, and the attributed instruction
execution time.
8-4
Instruction
#1) MOVE.L
#2) ADD.L
#3) MOVE.L
#4) ADD.L
Address n
n + 4
n + 8
M68020 USER'S MANUAL
D4,(A1)+
D4,D5
(A1), –(A2)
D5,D6
••• MOVE #1
ADD #2 MOVE #3
ADD #4 •••
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