Slave Ird; Hd Output Card With 3G-Sdi Support - Ericsson RX8000 Reference Manual

Integrated receivers/decoders
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Using the Equipment
The Frame Sync NTSC Offset or Frame Sync PAL Offset should be set to zero
pixel offset.
On the Output settings, Output One should be set to 3G-SDI and Output Two
should be set to ASI for daisy-chaining. The 3G-SDI Level can be set to the desired
level.
3.13.3.6.2

Slave IRD

On the Decode > Advanced settings, the Slave IRD is configured with Frame-Sync
ENABLED and the frame-sync signal is sourced from the Master IRD as described
above.
The 422 VSync Lock option must be ENABLED.
The Simul-Sync 3D license must be enabled and therefore any offset alignment
messages embedded in the video stream are picked up and applied by the Slave
IRD. Confirm this by ensuring that the status field Encoder Delay Compensation is
displayed.
The Rx Delay Mode option must be set to the same mode as set on the Master
IRD.
The Frame Sync NTSC Offset or Frame Sync PAL Offset should be set to zero
pixel offset. By default the Master IRD will output its quadrant slightly ahead of the
Slave IRDs due to propagation delay of the sync signal going through the analog
distribution amplifier. Normally this delay is minimal and does not cause any issues
with the synchronization of the four quadrants. However, to bring the receivers into
the closest possible alignment, the frame-sync on the Slave IRDs can be offset
using the above setting. If modified, the offset must be matched across all Slave
IRDs with the same value.
Note: As an example, configuring the Frame Sync PAL Offset with a value of
On the Output settings, Output One should be set to 3G-SDI and Output Two
should be set to ASI for daisy-chaining. The 3G-SDI Level must be set to the same
level as set on the Master IRD.
3.13.3.7

HD Output Card with 3G-SDI Support

Only certain hardware revisions of the HD Output card are capable of providing a
3G-SDI output. It should be determined that a HW-ID 1.2.1 or greater is fitted in
order to support 3G-SDI output.
3-210
+67 pixels corresponds to a delay of 1 micro-second. A negative value will
advance the signal output.
EN/LZT 790 0005 R7A

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