Notes On Ip Input Latency - Ericsson RX8000 Reference Manual

Using the Equipment
The IP layer is according to RFC791 – Internet Protocol Specification.
Figure 3.47 Building the Ethernet Frame
The setup and status of the IP Input is accessed through the main Input page from
the web interface or front panel.
3.10.5.6

Notes on IP Input Latency

FEC correction can be enabled or disabled on the card. When enabled and the
transmitter dispatches a valid ProMPEG FEC (Code of Practice issue 3 release),
FEC latency is introduced by the card. The latency introduced by card is directly
proportional to the FEC scheme configured at the source and is given by the
formula:
The current buffer level status is indicated in milliseconds based on the total buffer
memory internally allocated by the card. This status indicates the total latency
measured from the card's RJ-45 port to host. This status does not include picture
decoding latency introduced by host. Both buffer level and FEC latency are
configurable, allowing fine control of the card's latency.
Clock drift compensation introduces a small amount of latency. The exact amount of
latency is based upon the difference between the encoded video's clock rate and
the local clock rate.
The clock drift compensation should never be more than +/-5 ms. Typically, the
encoder and IRD clocks will never be the full 1620 Hz different and normally a
maximum compensation period of a couple of milliseconds is expected.
The maximum buffer size that should be configured is as follows (where bit rate is
specified in bits per second):
3-80
8H
20H Information
14H Information
FEC latency = 2 x Rows X Columns x packet period
Packet period = ((TS per IP) (188) +54) 8 / Bit rate
Current buffer level = Jitter Buffer + FEC latency + clock compensation
Max buffer level = (100000000-Bits required for FEC) / Bit rate
188
...
Information
188 TS packets (1 to7)
UDP datagram
IP datagram
Ethernet frame
EN/LZT 790 0005 R7A