Internal Pull-Up And Pull-Down Resistors On Jtag Pins; Swj Debug Port Connection With Standard Jtag Connector; Table 8. Debug Port Pin Assignment - ST STM32F4 Series Application Note

Debug management
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
JNTRST
5.2.2

Internal pull-up and pull-down resistors on JTAG pins

The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F4xxxx embeds internal pull-up and pull-
down resistors on JTAG input pins:
•
JNTRST: Internal pull-up
•
JTDI: Internal pull-up
•
JTMS/SWDIO: Internal pull-up
•
TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
•
JNTRST: Input pull-up
•
JTDI: Input pull-up
•
JTMS/SWDIO: Input pull-up
•
JTCK/SWCLK: Input pull-down
•
JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but
there is no special recommendation for TCK. However, for the STM32F4xxxx, an integrated
pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.
5.2.3

SWJ debug port connection with standard JTAG connector

Figure 14
connector.
30/50

Table 8. Debug port pin assignment

JTAG debug port
Type
JTAG test mode
I
selection
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test nReset
shows the connection between the STM32F4xxxx and a standard JTAG
Description Type
I/O
I
-
-
-
AN4488 Rev 7
SW debug port
Debug assignment
Serial wire data
input/output
Serial wire clock
-
TRACESWO if async
trace is enabled
-
AN4488
Pin
assignmen
t
PA13
PA14
PA15
PB3
PB4