Table of Contents
Advertisement
CHAPTER 3 CLOCK CONTROLLER
3.8 Configuration of Prescaler
3.8
Configuration of Prescaler
Figure 3.8-1 is the block diagram of the prescaler.
■ Block Diagram of Prescaler
MCLK (machine clock)
7
F
/2
F
/2
CH
CRH
From
or
time-base
timer
8
F
/2
F
/2
CH
CRH
MCLK
F
CH
F
CRH
F
MCRPLL
•
5-bit counter
This counter counts the machine clock (MCLK) and outputs the count value to the output
control circuit.
•
Output control circuit
Based on the 5-bit counter value, this circuit supplies clocks generated by dividing the
machine clock (MCLK) by 2, 4, 8, 16, or 32 to individual peripheral functions. The circuit
also buffers the clock from the time-base timer (F
F
MCRPLL
■ Input Clock
The prescaler uses the machine clock, or the output clock of the time-base timer as the input
clock.
■ Output Clock
The prescaler supplies clocks to the following peripheral functions:
•
8/16-bit composite timer
•
8/10-bit A/D converter
•
8/16-bit PPG
•
16-bit PPG timer
•
16-bit reload timer
•
UART/SIO dedicated baud rate generator
56
Figure 3.8-1 Block Diagram of Prescaler
5-bit
counter
6
6
F
/2
MCRPLL
or
7
7
F
/2
MCRPLL
: Machine clock (internal operating frequency)
: Main clock frequency
: Main CR clock frequency
: Main CR PLL clock frequency
6
7
/2
, or F
/2
) and supplies it to peripheral functions.
MCRPLL
FUJITSU SEMICONDUCTOR LIMITED
Prescaler
Counter value
Output
control circuit
CH
MB95630H Series
MCLK/2
MCLK/4
Count
MCLK/8
clock
MCLK/16
source
to
MCLK/32
different
peripheral
functions
7
6
6
F
/2
, F
/2
or F
/2
CH
CRH
MCRPLL
8
7
7
F
/2
, F
/2
or F
/2
CH
CRH
MCRPLL
7
8
6
/2
, F
/2
, F
/2
, F
CH
CRH
MN702-00009-2v0-E
7
/2
,
CRH
Hide quick links:
Advertisement
Table of Contents
