Standby Control Register (Stbc) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 3 CPU
3.7.4

Standby Control Register (STBC)

The standby control register (STBC) controls transition to sleep /stop modes, pin state
settings in stop mode, and software reset.
■
Standby Control Register (STBC)
Address bit7
0008 STP
H
R/W
: Readable/Writable
R/W
: Read only
R
: Unused
: Initial value
66
Figure 3.7-1 Standby Control Register (STBC)
bit6 bit5 bit4 bit3
SLP SPL RST RESV
R/W R/W R/W R
Initial value
bit2 bit1 bit0
00010---
RESV
When read
0 Always "0"
1
RST
When read
0
1
Always "1"
Pin state setting bit
SPL
Pin states applied are maintained in stop mode.
0
1 Pin states are set to Hi-Z in stop mode.
SLP
When read
0 Always "0"
1
STP
When read
Always "0"
0
1
B
Reserved bit
When written
Does not affect operations
Software reset bit
When written
4-instruction reset signal
generated.
Does not affect operations
Sleep bit
When written
Does not affect operations
Transition to sleep mode
Stop bit
When written
Does not affect operations
Transition to stop mode