Timebase Timer Clear Register (Ctbr) - Fujitsu MB91F109 FR30 Hardware Manual

3.5

Timebase Timer Clear Register (CTBR)

The timebase timer clear register (CTBR) clears the timebase timer to 0 for
initialization.
Configuration of the Timebase Timer Clear Register (CTBR)
The configuration of the timebase timer clear register (CTBR) is shown below:
00000483
Bit Functions of the Timebase Timer Clear Register (CTBR)
[bit 07 to bit 00]
When A5
0 immediately after 5A
no restriction on the time interval between A5
<Note>
Clearing the timebase timer using this register temporarily changes the oscillation stabilization
wait time, watchdog cycle, and cycles of the peripherals using the time base.
07 06 05
D7 D6 D5
H
and 5A are written successively to this register, the timebase timer is cleared to
H H
is written. The value read from this register is undefined. There is
H
3.5 Timebase Timer Clear Register (CTBR)
04 03 02 01
D4 D3 D2 D1
and 5A
H
00
Initial value Access
D0 XXXXXXXX W
writing.
H
81