Operations And Setting Procedure Example - Fujitsu 8FX Hardware Manual

CHAPTER 7 TIME-BASE TIMER
7.4 Operations and Setting Procedure
Example
7.4

Operations and Setting Procedure Example

This section describes the operations of the interval timer function of the time-
base timer.
■ Operations of Time-base Timer
The counter of the time-base timer is initialized to "0xFFFFFF" after a reset, and starts
counting while being synchronized with the main clock divided by two, or with the main CR
clock or with the main CR PLL clock.
The time-base timer continues to count down as long as the main clock, the main CR clock or
the main CR PLL clock is oscillating. Once the main clock, the main CR clock or the main CR
PLL clock stops, the counter stops counting and is initialized to "0xFFFFFF".
To use the interval timer function, do the settings shown in Figure 7.4-1.
TBTC
When the time-base timer clear bit in the time-base timer control register (TBTC:TCLR) is set
to "1", the counter of the time-base timer is initialized to "0xFFFFFF" and continues to count
down. When the selected interval time has elapsed, the time-base timer interrupt request flag
bit in the time-base timer control register (TBTC:TBIF) becomes "1". In other words, an
interrupt request is generated at each interval time selected, based on the time when the counter
was last cleared.
■ Clearing Time-base Timer
With the output of the time-base timer being used in other peripheral functions, clearing the
time-base timer affects their operations in various ways such as changing the count time of a
peripheral function.
When clearing the counter by using the time-base timer clear bit (TBTC:TCLR), modify the
settings of other peripheral functions whenever necessary so that clearing the counter does not
have any unexpected effect on them.
When the output of the time-base timer is selected as the count clock for the watchdog timer,
clearing the time-base timer also clears the watchdog timer.
The time-base timer is cleared not only by the TCLR bit, but also when the main clock, the
main CR clock, or the main CR PLL clock is stopped and the oscillation stabilization wait time
is necessary. The time-base timer is cleared in the following situations:
• The device transits from the main clock mode, the main CR clock mode or the main CR
PLL clock mode to the stop mode.
• The device transits from the main clock mode, the main CR clock mode or the main CR
PLL clock mode to the subclock mode or the sub-CR clock mode.
• At power-on
• At low-voltage detection reset
92
Figure 7.4-1 Settings of Interval Timer Function
bit7 bit6 bit5
TBIF TBIE -
0 1
: Bit to be used
1 : Set to "1".
0 : Set to "0".
FUJITSU SEMICONDUCTOR LIMITED
bit4 bit3 bit2
TBC3 TBC2 TBC1
MB95630H Series
bit1 bit0
TBC0 TCLR
0
MN702-00009-2v0-E