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II CORE BLOCK: BCU (Bus Control Unit)
DRAM Direct Interface
Outline of DRAM Interface
The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or
areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11
bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to
areas) as well as random cycles. The refresh method (CAS-before-RAS refresh or self-refresh) and timing
conditions (e.g., number of RAS/CAS cycles and number of precharge cycles) can be programmed using a control
bit.
When selecting areas 8 and 7 or areas 14 and 13 to be used for DRAM, it depends on chip-enable settings using
CEFUNC (D9) / DRAM timing set-up register (0x48130).
CEFUNC = "00": DRAM can be connected to areas 8 and 7 (default)
#CE8 and #CE7 function as #RAS0 and #RAS1, respectively.
CEFUNC "00": DRAM can be connected to areas 14 and 13.
#CE14 and #CE13 function as #RAS2 and #RAS3, respectively.
Figure 4.27 shows a sample DRAM connection. Table 4.15 and Table 4.16 show examples of connectable DRAMs
and typical configurations.
DRAM
1M (64K x 16)
4M (256K x 16)
16M (1M x 16)
Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details.
B-II-4-24
S1C33
A[9:1]
D[15:0]
#RD
#RASx(#CEx)*
#HCAS
#LCAS
#WE
x: 14, 13, 8 or 7
Figure 4.27 Sample DRAM Connection
Table 4.15 Connectable DRAM Example
Number of
Number of
devices
Row bits
1
1
1
Table 4.16 DRAM Configuration Example (areas 7 and 8 only)
Area 7
Area 8
1 I/O
DRAM (1M)
2 I/O
DRAM (4M)
3 I/O
DRAM (16M)
4 DRAM (1M)
DRAM (1M)
5 DRAM (4M)
DRAM (4M)
6 DRAM (16M)
DRAM (16M)
4M DRAM
(256K x 16)
A[8:0]
I/O[15:0]
#OE
#RAS
#HCAS
#LCAS
#WE
Number of
Column bits
8
8
9
9
12
8
Total memory size
1M bits
(128K bytes)
4M bits
(512K bytes)
16M bits
(2M bytes)
2M bits
(256K bytes)
8M bits
(1M bytes)
32M bits
(4M bytes)
EPSON
Memory size
128K bytes
512K bytes
2M bytes
S1C33L03 FUNCTION PART
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