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A.6 8255A
8255A interface setup examples
Operating
frequency
Wait cycle
20MHz
25MHz
33MHz
8255A interface timing
SRAM interface
Parameter
<Read cycle>
Read cycle time
Address access time
#CE access time
#OE access time
Output disable delay time
<Write cycle>
Write cycle time
Address enable time
Write pulse width
Input data setup time
Input data hold time
1 The S1C33L03 enables up to 7 cycles of wait-cycle insertion. If a number of wait cycles more than 7 cycles
needs to be inserted, input the #WAIT signal from external hardware. Note that the interface must be set for
SRAM type devices to insert wait cycles using the #WAIT pin. (Refer to "BCU (Bus Control Unit)" in the
"S1C33L03 FUNCTION PART", for more information.)
2 This setting cannot satisfy the 150 ns of output-disable delay time specification required for the 8255A. When
implementing such a low-speed device in the system, the external bus must be separated by inserting a 3-state
bus buffer at the output side (when viewed from the CPU) of the external system bus.
3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the
external data bus D[15:0] or by inserting a latch at the output side of the external system interface.
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
Read cycle
Read cycle
9
1
10
11
12
14
15
Symbol
Min.
t
300
RC
t
–
ACC
t
–
ACS
t
–
OE
t
10
OHZ
t
430
WC
t
400
AW
t
400
WP
t
100
DW
t
3
30
DH
EPSON
Output disable
Write cycle
delay cycle
10
3.5
12
3.5
15
3.5
33MHz
Max.
Cycle
Time
Cycle
–
15
450
12
250
15
450
12
250
15
450
12
250
14.5
435
11.5
150
3.5
105
3.5
–
15
450
12
–
14.5
435
11.5
–
14
420
11
–
14
420
11
–
0.5
15
0.5
2
25MHz
20MHz
Time
Cycle
Time
480
10
500
480
10
500
480
10
500
460
9.5
475
140
3.5
175
480
10
500
460
9.5
475
440
9
450
440
9
450
20
0.5
25
A-127
A-1
A-ap
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