Programming Notes - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Cmos 32-bit single chip microcomputer
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Programming Notes

(1) After an initial reset, the interrupt factor flags become indeterminate. To prevent generation of an unwanted
interrupt or IDMA request, be sure to reset the flags in a program.
(2) To prevent regeneration of interrupts due to the same factor following the occurrence of an interrupt, always
be sure to reset the interrupt factor flag before resetting the PSR or executing the reti instruction.
(3) The input/output ports operate only when the prescaler is operating.
(4) When restarting from the SLEEP or HALT2 state, interrupt input from a port can be used as a trigger, but
functionally, this interrupt input operates as level input. Therefore, a level input based restart is performed
even in the case of set edge input.
Restart operation is as follows for rising and falling edges.
In case of rising edge interrupt setting: Restarted by high level input.
In case of falling edge interrupt setting: Restarted by low level input.
In normal operation, a restart begins following the elapse of a given time after execution of the SLP
instruction, but when restart by a falling (rising) level (edge) is set, the operation is as follows.
• The restart is effected immediately after execution of the SLP instruction.
• As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge,
and therefore the SLEEP state is entered only momentarily, and the restart is effected immediately
afterwards.
There was a synchronization circuit using a clock signal in the port input circuit, and as the clock is stopped
in the SLEEP state and the clock can be stopped in the HALT2 state, the configuration provided for this
synchronization circuit to be bypassed when restarting. Therefore, a restart is effected when the input level
from a port is active by level. Consequently, the system design should assume that a restart by means of port
input from the SLEEP state or HALT2 state is performed by level.
S1C33L03 FUNCTION PART
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
EPSON
A-1
B-III
I/O
B-III-9-25

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