Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 464

V DMA BLOCK: HSDMA (High-Speed DMA)
Register name Address Bit
High-speed 0048254 DF
DMA Ch.3 (HW) DE
low-order DD
source address DC
set-up register DB
DA
Note:
D9
D) Dual address
D8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed 0048256 DF
DMA Ch.3 (HW) DE
high-order DD
source address DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
D8
mode
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048258 DF
DMA Ch.3 (HW) DE
low-order DD
destination DC
address set-up DB
register DA
D9
Note:
D8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
B-V-2-26
Name Function
S3ADRL15 D) Ch.3 source address[15:0]
S3ADRL14 S) Ch.3 memory address[15:0]
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
– reserved
DATSIZE3 Ch.3 transfer data size
S3IN1 D) Ch.3 source address control
S3IN0 S) Ch.3 memory address control
S3ADRH11 D) Ch.3 source address[27:16]
S3ADRH10 S) Ch.3 memory address[27:16]
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
D3ADRL15 D) Ch.3 destination address[15:0]
D3ADRL14 S) Invalid
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
Setting
–
1 Half word 0 Byte
S3IN[1:0] Inc/dec
1 1 Inc.(no init)
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
EPSON
Init. R/W Remarks
X R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
– –
0 R/W
0 R/W
0
X R/W
X
X
X
X
X
X
X
X
X
X
X
X R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S1C33L03 FUNCTION PART