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Notes on Standby Mode
Interrupts
The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used
for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE
(interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt.
Otherwise, the standby mode cannot be canceled even when an interrupt occurs. Refer to "ITC (Interrupt
Controller)", for interrupt settings.
Oscillation circuit
The high-speed (OSC3) oscillation circuit stops in SLEEP mode and restarts oscillating when SLEEP mode is
canceled. If the CPU had operated with the OSC3 clock before entering SLEEP mode, the CPU restarts
operating with the OSC3 clock immediately after canceling SLEEP mode. However, the OSC3 oscillation
needs appropriate stabilization time (10 ms max. under the standard condition in 3.3 V). To restart the CPU
after the oscillation stabilizes, a programmable interval can be inserted between cancellation of SLEEP mode
and starting the CPU operation. Refer to "CLG (Clock Generator)", for details.
The oscillation start time of the high-speed (OSC3) oscillation circuit varies according to the components to
be used, board pattern and operating environment. The interval must be set to allow enough margin.
BCU
When the CPU enters the standby mode, the BCU (bus control unit) stops after the current bus cycle has
completed. All the chip enable signals are negated.
In basic HALT mode, the BCLK (bus clock) signal is output and DRAM refresh cycles are generated. DMA
also operates.
In HALT2 or SLEEP mode, the BCLK signal stops, therefore DRAM refresh cycles cannot be generated and
DMA stops.
Additional
The contents of the CPU registers and input/output port status are retained in the standby mode. Almost all
control and data registers of the internal peripheral circuits are also retained, note, however, some registers
may be changed at the transition to SLEEP mode. Refer to the section of each peripheral circuit for other
precautions.
Test Mode
The C33 Core Block has the ICEMD pin for testing the chip. When this pin is set to High, the IC enters the
following state:
• All output pins go into high-impedance state except for the clock output pins (OSC2: H, OSC4 H, PLLC: L).
• Clock inputs are disabled. OSC1, OSC3 and PLL stop operating. OSC2: H, OSC4 H, PLLC: L
• All the pull-up and pull-down resistors enter an inactive state.
Leave this pin open or connect to V
Debug Mode
The C33 Core Block supports the debug mode.
The debug mode is a CPU function, and realizes single step operation and break functions in the chip itself. Refer
to the "S1C33000 Core CPU Manual" for details of the debug mode and the functions.
Area 2 in the memory map can only be accessed in the debug mode.
In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed
(OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the
debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating.
S1C33L03 FUNCTION PART
for normal operation. The ICEMD pin has a built-in pull-down resistor.
SS
EPSON
II CORE BLOCK: CPU AND OPERATING MODE
A-1
B-II
CPU
B-II-2-3
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