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Interrupt enable register
This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this
register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding
interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding
interrupt factor occurs.
Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset
by writing "0" and set by writing "1". By reading this register, its setup status can be checked at any time.
Settings of the interrupt enable register do not affect the operation of interrupt factor flags, so when an
interrupt factor occurs the interrupt factor flag is set to "1" even if the corresponding interrupt enable bit is set
to "0".
When initially reset, the interrupt enable register is set to "0" (interrupts are disabled).
In cases when IDMA is started up by occurrence of an interrupt factor or when clearing standby mode
(HALT or SLEEP mode) too, the corresponding interrupt enable bit must be set to "1".
The interrupt controller outputs an interrupt request to the CPU when the following conditions are met:
• An interrupt factor has occurred and the interrupt factor flag is set to "1".
• The bit of the interrupt enable register for the interrupt factor that has occurred is set to "1" (interrupt enable).
• The bit of the IDMA request register for the interrupt factor that has occurred is set to "0" (interrupt request).
If two or more interrupt factors occur simultaneously, the interrupt factor that has the highest priority is allowed to
signal an interrupt request to the CPU. (See the following section.)
When these conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with
the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector
number.
These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt
enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs.
They are not cleared if the CPU simply accepts the interrupt request.
S1C33L03 FUNCTION PART
II CORE BLOCK: ITC (Interrupt Controller)
EPSON
A-1
B-II
ITC
B-II-5-7
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