Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 591

Register name Address Bit
Serial I/F Ch.2 00401F3 D7
control register (B) D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 00401F4 D7–5
IrDA register (B) D4
D3
D2
D1
D0
Serial I/F Ch.3 00401F5 D7
transmit data (B) D6
register D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 00401F6 D7
receive data (B) D6
register D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 00401F7 D7–6
status register (B) D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 00401F8 D7
control register (B) D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 00401F9 D7–5
IrDA register (B) D4
D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
TXEN2 Ch.2 transmit enable
RXEN2 Ch.2 receive enable
EPR2 Ch.2 parity enable
PMD2 Ch.2 parity mode selection
STPB2 Ch.2 stop bit selection
SSCK2 Ch.2 input clock selection
SMD21 Ch.2 transfer mode selection
SMD20
– reserved
DIVMD2 Ch.2 async. clock division ratio
IRTL2 Ch.2 IrDA I/F output logic inversion
IRRL2 Ch.2 IrDA I/F input logic inversion
IRMD21 Ch.2 interface mode selection
IRMD20
TXD37 Serial I/F Ch.3 transmit data
TXD36 TXD37(36) = MSB
TXD35 TXD30 = LSB
TXD34
TXD33
TXD32
TXD31
TXD30
RXD37 Serial I/F Ch.3 receive data
RXD36 RXD37(36) = MSB
RXD35 RXD30 = LSB
RXD34
RXD33
RXD32
RXD31
RXD30
– reserved
TEND3 Ch.3 transmit-completion flag
FER3 Ch.3 flaming error flag
PER3 Ch.3 parity error flag
OER3 Ch.3 overrun error flag
TDBE3 Ch.3 transmit data buffer empty
RDBF3 Ch.3 receive data buffer full
TXEN3 Ch.3 transmit enable
RXEN3 Ch.3 receive enable
EPR3 Ch.3 parity enable
PMD3 Ch.3 parity mode selection
STPB3 Ch.3 stop bit selection
SSCK3 Ch.3 input clock selection
SMD31 Ch.3 transfer mode selection
SMD30
– reserved
DIVMD3 Ch.3 async. clock division ratio
IRTL3 Ch.3 IrDA I/F output logic inversion
IRRL3 Ch.3 IrDA I/F input logic inversion
IRMD31 Ch.3 interface mode selection
IRMD30
EPSON
Setting Init. R/W
1 Enabled 0 Disabled 0
1 Enabled 0 Disabled 0
1 With parity 0 No parity X
1 Odd 0 Even X
1 2 bits 0 1 bit X
1 #SCLK2 0 Internal clock X
SMD2[1:0] Transfer mode X
1 1 8-bit asynchronous X
1 0 7-bit asynchronous
0 1 Clock sync. Slave
0 0 Clock sync. Master
– –
1 1/8 0 1/16 X
1 Inverted 0 Direct X
1 Inverted 0 Direct X
IRMD2[1:0] I/F mode X
1 1 reserved X
1 0 IrDA 1.0
0 1 reserved
0 0 General I/F
0x0 to 0xFF(0x7F) X
X
X
X
X
X
X
X
0x0 to 0xFF(0x7F) X
X
X
X
X
X
X
X
– –
1 Transmitting 0 End 0
1 Error 0 Normal 0
1 Error 0 Normal 0
1 Error 0 Normal 0
1 Empty 0 Buffer full 1
1 Buffer full 0 Empty 0
1 Enabled 0 Disabled 0
1 Enabled 0 Disabled 0
1 With parity 0 No parity X
1 Odd 0 Even X
1 2 bits 0 1 bit X
1 #SCLK3 0 Internal clock X
SMD3[1:0] Transfer mode X
1 1 8-bit asynchronous X
1 0 7-bit asynchronous
0 1 Clock sync. Slave
0 0 Clock sync. Master
– –
1 1/8 0 1/16 X
1 Inverted 0 Direct X
1 Inverted 0 Direct X
IRMD3[1:0] I/F mode X
1 1 reserved X
1 0 IrDA 1.0
0 1 reserved
0 0 General I/F
APPENDIX: I/O MAP
A-1
Remarks
R/W
R/W
R/W Valid only in
R/W asynchronous mode.
R/W
R/W
R/W
– 0 when being read.
R/W
R/W Valid only in
R/W asynchronous mode.
R/W
R/W
R
– 0 when being read.
R
R/W Reset by writing 0.
R/W Reset by writing 0.
R/W Reset by writing 0.
R
R
R/W
R/W
R/W Valid only in
R/W asynchronous mode.
R/W
R/W
R/W
– 0 when being read.
R/W
R/W Valid only in
R/W asynchronous mode.
R/W
B-ap
B-APPENDIX-11