Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 507

Timing setup
The following parameters can be set in conformity with SDRAM specifications before use.
Symbol
t ACTIVE to ACTIVE command period
RC
AUTO REFRESH command period
Exit SELF REFRESH to ACTIVE command period
t ACTIVE to PRECHARGE command period
RAS
Minimum SELF REFRESH period
t ACTIVE to READ or WRITE delay time
RCD
t PRECHARGE command period
RP
t ACTIVE bank (a) to ACTIVE bank (b) period
RRD
t MODE REGISTER SET cycle time
RSC
BCLK
Command
SDBA[1:0]
SDA[12:11, 9:0]
SDA10
DQ[15:0]
BCLK
Command
SDBA[1:0]
SDA[12:11, 9:0]
SDA10
DQ[15:0]
Note: When the auto-refresh command is executed, the following command may be issued 3 or 4
CPU_CLK cycles from that point regardless of the t
(D[2:0])/SDRAM timing set-up register 1 (0x39FFC4). Therefore, use SDRAMs with 75 ns or less
of t .
RC
S1C33L03 FUNCTION PART
Table 2.10 SDRAM Parameters
SDRAM parameter
NOP ACTV NOP READ
BA BA
ROW COL
ROW
t
RCD
(a) Burst read
NOP ACTV NOP READ
BAa BAa
ROWa COLa
ROWa
t
RRD
(b) Bank interleaved access
Figure 2.7 SDRAM Parameters
EPSON
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Set values
(# of clocks)
1 to 8 SDRTRC[2:0] (D[2:0])/SDRAM
timing set-up register 1 (0x39FFC4)
1 to 8 SDRTRAS[2:0] (D[7:5])/SDRAM
timing set-up register 1 (0x39FFC4)
1 to 4 SDRTRCD[1:0] (D[7:6])/SDRAM
timing set-up register 2 (0x39FFC5)
1 to 4 SDRTRP[1:0] (D[4:3])/SDRAM
timing set-up register 1 (0x39FFC4)
1 to 4 SDRTRRD[1:0] (D[4:3])/SDRAM
timing set-up register 2 (0x39FFC5)
1 or 2 SDRTRSC (D5)/SDRAM timing set-
up register 2 (0x39FFC5)
NOP NOP NOP PRE NOP ACTV
BA
BKsel
DATA DATA DATA DATA
CAS latency
t t
RAS
t
RC
(Burst length = 4)
NOP ACTV NOP READ NOP
BAb BAb
ROWb COLb
ROWb
Da Da Da Da
+1 +2
(Burst length = 4)
value set in the SDRTRC[2:0]
RC
Control bits
BA
ROW
ROW
RP
NOP
Db
+3
B-VI-2-11
A-1
B-VI
SDRAM