Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 213

Register name Address Bit
DRAM timing 0048130 DF–C
set-up register (HW) DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access control 0048132 DF
register (HW) DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G/A read signal 0048138 DF
control register (HW) DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BCLK select 004813A D7–4
register (B) D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
– reserved
A3EEN Area 3 emulation
CEFUNC1 #CE pin function selection
CEFUNC0
CRAS Successive RAS mode setup
RPRC1 DRAM
RPRC0 RAS precharge cycles selection
– reserved
CASC1 DRAM
CASC0 CAS cycles selection
– reserved
RASC1 DRAM
RASC0 RAS cycles selection
A18IO Area 18, 17 internal/external access
A16IO Area 16, 15 internal/external access
A14IO Area 14, 13 internal/external access
A12IO Area 12, 11 internal/external access
– reserved
A8IO Area 8, 7 internal/external access
A6IO Area 6 internal/external access
A5IO Area 5, 4 internal/external access
A18EC Area 18, 17 endian control
A16EC Area 16, 15 endian control
A14EC Area 14, 13 endian control
A12EC Area 12, 11 endian control
A10EC Area 10, 9 endian control
A8EC Area 8, 7 endian control
A6EC Area 6 endian control
A5EC Area 5, 4 endian control
A18AS Area 18, 17 address strobe signal
A16AS Area 16, 15 address strobe signal
A14AS Area 14, 13 address strobe signal
A12AS Area 12, 11 address strobe signal
– reserved
A8AS Area 8, 7 address strobe signal
A6AS Area 6 address strobe signal
A5AS Area 5, 4 address strobe signal
A18RD Area 18, 17 read signal
A16RD Area 16, 15 read signal
A14RD Area 14, 13 read signal
A12RD Area 12, 11 read signal
– reserved
A8RD Area 8, 7 read signal
A6RD Area 6 read signal
A5RD Area 5, 4 read signal
– reserved
A1X1MD Area 1 access-speed
– reserved
BCLKSEL1 BCLK output clock selection
BCLKSEL0
EPSON
II CORE BLOCK: BCU (Bus Control Unit)
Setting Init. R/W
– –
1 Internal ROM 0 Emulation 1
CEFUNC[1:0] #CE output 0
1 x #CE7/8..#CE17/18 0
0 1 #CE6..#CE17
0 0 #CE4..#CE10
1 Successive 0 Normal 0
RPRC[1:0] Number of cycles 0
1 1 4 0
1 0 3
0 1 2
0 0 1
– –
CASC[1:0] Number of cycles 0
1 1 4 0
1 0 3
0 1 2
0 0 1
– –
RASC[1:0] Number of cycles 0
1 1 4 0
1 0 3
0 1 2
0 0 1
1 Internal 0 External 0
access access 0
0
0
– 0
1 Internal 0 External 0
access access 0
0
1 Big endian 0 Little endian 0
0
0
0
0
0
0
0
1 Enabled 0 Disabled 0
0
0
0
– 0
1 Enabled 0 Disabled 0
0
0
1 Enabled 0 Disabled 0
0
0
0
– 0
1 Enabled 0 Disabled 0
0
0
– 0
1 2 cycles 0 4 cycles 0
– 0
BCLKSEL[1:0] BCLK 0
1 1 PLL_CLK 0
1 0 OSC3_CLK
0 1 BCU_CLK
0 0 CPU_CLK
A-1
Remarks
– 0 when being read.
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
– 0 when being read.
R/W
B-II
R/W
R/W
R/W
R/W
– 0 when being read.
BCU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
R/W
– 0 when being read.
R/W x2 speed mode only
– 0 when being read.
R/W
B-II-4-37