Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 615

Register name Address Bit
High-speed 0048220 DF
DMA Ch.0 (HW) DE
transfer DD
counter DC
register DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048222 DF
DMA Ch.0 (HW) DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed 0048224 DF
DMA Ch.0 (HW) DE
low-order DD
source address DC
set-up register DB
DA
Note:
D9
D) Dual address
D8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed 0048226 DF
DMA Ch.0 (HW) DE
high-order DD
source address DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
D8
mode
D7
D6
D5
D4
D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
TC0_L7 Ch.0 transfer counter[7:0]
TC0_L6 (block transfer mode)
TC0_L5
TC0_L4 Ch.0 transfer counter[15:8]
TC0_L3 (single/successive transfer mode)
TC0_L2
TC0_L1
TC0_L0
BLKLEN07 Ch.0 block length
BLKLEN06 (block transfer mode)
BLKLEN05
BLKLEN04 Ch.0 transfer counter[7:0]
BLKLEN03 (single/successive transfer mode)
BLKLEN02
BLKLEN01
BLKLEN00
DUALM0 Ch.0 address mode selection
D0DIR D) Invalid
S) Ch.0 transfer direction control
– reserved
TC0_H7 Ch.0 transfer counter[15:8]
TC0_H6 (block transfer mode)
TC0_H5
TC0_H4 Ch.0 transfer counter[23:16]
TC0_H3 (single/successive transfer mode)
TC0_H2
TC0_H1
TC0_H0
S0ADRL15 D) Ch.0 source address[15:0]
S0ADRL14 S) Ch.0 memory address[15:0]
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
– reserved
DATSIZE0 Ch.0 transfer data size
S0IN1 D) Ch.0 source address control
S0IN0 S) Ch.0 memory address control
S0ADRH11 D) Ch.0 source address[27:16]
S0ADRH10 S) Ch.0 memory address[27:16]
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
EPSON
Setting Init. R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 Dual addr 0 Single addr 0
– –
1 Memory WR 0 Memory RD 0
– –
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
– –
1 Half word 0 Byte 0
S0IN[1:0] Inc/dec 0
1 1 Inc.(no init) 0
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
X
X
X
X
X
X
X
X
X
X
X
X
APPENDIX: I/O MAP
A-1
Remarks
R/W
R/W
R/W
–
R/W
– Undefined in read.
R/W
R/W
–
R/W
R/W
R/W
B-ap
B-APPENDIX-35