Table of Contents
Advertisement
V DMA BLOCK: HSDMA (High-Speed DMA)
Register name
Address
Bit
High-speed
0048234
DF
DMA Ch.1
(HW)
DE
low-order
DD
source address
DC
set-up register
DB
DA
Note:
D9
D) Dual address
D8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed
0048236
DF
DMA Ch.1
(HW)
DE
high-order
DD
source address
DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
D8
mode
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
0048238
DF
DMA Ch.1
(HW)
DE
low-order
DD
destination
DC
address set-up
DB
register
DA
D9
Note:
D8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
B-V-2-22
Name
Function
S1ADRL15
D) Ch.1 source address[15:0]
S1ADRL14
S) Ch.1 memory address[15:0]
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
–
reserved
DATSIZE1
Ch.1 transfer data size
S1IN1
D) Ch.1 source address control
S1IN0
S) Ch.1 memory address control
S1ADRH11
D) Ch.1 source address[27:16]
S1ADRH10
S) Ch.1 memory address[27:16]
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
D1ADRL15
D) Ch.1 destination address[15:0]
D1ADRL14
S) Invalid
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
Setting
–
1 Half word
0 Byte
S1IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
Fixed
EPSON
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
–
–
0
R/W
0
R/W
0
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S1C33L03 FUNCTION PART
Advertisement
Table of Contents
